Luck is great, but most of life is hard work
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I am a Computer Engineering Master's student at Texas A\&M University. I aspire to specialize in VLSI systems and digital design to augment my knowledge in the developement of system on chip, the core hardware component that drives the growth of Internet of Things and meets the complex computational demands of today. I intend to pursue industrial research towards acheiving differentiated, optimized and reliable solutions in the field of integarted circuits to contribute towards emerging technological trends

I believe that the semiconductor industries have a huge role to play in the society. The hunger for faster, smaller and power effecient chips never recedes. With these requisites come more challenges in realizing a system on chip with emerging technology. I look forward to address these in my research career. With the right background in understanding its importance to learning the current limitations in the field of VLSI and computer architecture, I am committed to learn and work towards a better technological tomorrow.

Work experience

I have three years of work experience as a Design Engineer at Texas Instruments. I was part of a team that develops low power SOCs with multiple sleep modes for industrial applications. My prime responsibility was a quality handoff of SOC to the synthesis team.

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I interacted with multiple teams geographically located across globe to understand IP functionaltiy and to successfully integrate them into a SOC using tools such as autogen and magillem. This also required me to design a glue-logic block that would handle any synchronization requirements between IPs.

During the process, I developed expertise in IPXACT-1685 standards, which is a skeleton representation of an IP used by integration tools. I used this expertise to identify and develop automated checkers for IP handoff that was used across teams.

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A quality SOC handoff also means to ensure the design is free of errors and bugs.

I handled the SOC lint check using spyglass tool. It is used to identify potential bugs in an early stage such as incomplete case or if statements that can result in latches, potential simulation vs synthesis mismatches that results in logic behaving differently than as expected and design constructs that are non-synthesizable.

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Low power SOC has multiple sleep modes that the user can configure according to its application.

I worked in a team of 4 to verify SOC during these sleep modes using Cadence NCSIM. The goal was to ensure that the system can enter and exit sleep modes gracefully. System level scenarios were targetted to also check the time to enter and exit sleep modes does not violate system specifications.

During sleep modes, a part of the SOC is shut off while the remaining is still on. The ON system must function as usual. This requires isolation of the ON system from the OFF system. I developed automatic creation of isolation checkers using perl and CPF that verifies the correctness of these isolations. This helped in catching issues during early design cycle.

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Besides SOC design and verification, I had the opportunity to work on architecture analysis and design of instruction cache. I performed analysis based on cache hits/misses as a trade off between area, power and performance using industrial standard benchmarks such as Coremark and Dhrystone. My main area of focus was to design a cache that would handle cycle dependencies keeping area and power minimal.

Projects

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ITTAGE - Indirect branch predictor

ITTAGE (Indirect Target TAgged GEometric length predictor) is the state of the art indirect branch target predictor. It uses multiple prediction tables hashed using global branch history and PC to achieve an unprecedented level of accuracy. The use of geometric lenghts allows the predictor to use correlation with large global history bits range. The use of multiple tables enables in exploiting correlation with small as well as long history bits. This project is an implmentation of it in C++ acheiving a speedup of 93%. Enhancements on the project were:

1. Base table improvement: Base table of ITTAGE is indexed from PC. This implementation proposes to index base table with a hash function of PC and previous target. This improves performance on benchmarks that have less correlation with conditional branch bits from global history to acheive an overall speedup of 5.3% on SPEC CPU 2006 traces.

2. Altpred: Altpred (alternate prediction) is the target used when the confidence on the predicted taregt is low in ITTAGE. The confidence comes from the confidence counter which are incemented when the prediction is right and decremented otherwise. This implementation proposes to use the main prediction itself when the confidence on altpred is low too. This proposal seems to improve overall performance, but not significantly.

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Perceptron based cache reuse predictor

Effect of large penalty caused by a miss on last level cache gives rise to the need for a better replacement policy. Perceptron based reuse prediction is used to identify dead blocks in the cache- blocks predicted not to be referenced again.

This algorithm learns from a few sampled sets and generalizes it to the entire cache, thereby reducing area and power. Its key features include its ability to learn and predict faster as the sampling algorithm is only updated on a reference to sampler sets. This project is implemented in C++ and acheives an overall geometric mean speedup of 6.4% on SPEC CPU 2006 benchmarks.

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Hardware Software Co-design

Created an IR receiver in hardware that tests, receives and decodes a IR signal. The decoding logic is implemented in Verilog on Xilinx FPGA board. An interrupt based device driver is developed in Linux environment to print out the decoded message onto the display.

Publications

A formal approach towards early RTL quality checks

2017 Cadence Club Formal Conference, Bangalore, India

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Checkpoint Simulation on SOC

2013 Texas Instruments Poster Presentations, Bangalore, India